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| a High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch ADG3257 FUNCTIONAL BLOCK DIAGRAM 1A 1B1 1B2 2B1 2A 2B2 3A 3B1 3B2 4A 4B1 4B2 FEATURES 100 ps Propagation Delay through the Switch 2 Switches Connect Inputs to Outputs Data Rates up to 933 Mbps Single 3.3 V/5 V Supply Operation Level Translation Operation Ultralow Quiescent Supply Current (1 nA Typical) 3.5 ns Switching Standard `3257 Type Pinout APPLICATIONS Bus Switching Bus Isolation Level Translation Memory Switching/Interleaving LOGIC BE S GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3257 is a CMOS bus switch comprised of four 2:1 multiplexers/demultiplexers with high impedance outputs. The device is manufactured on a CMOS process. This provides low power dissipation yet high switching speed and very low ON resistance, allowing the inputs to be connected to the outputs without adding propagation delay or generating additional ground bounce noise. The ADG3257 operates from a single 3.3 V/5 V supply. The control logic for each switch is shown in Table I. These switches are bidirectional when ON. In the OFF condition, signal levels are blocked up to the supplies. This bus switch is suited to both switching and level translation applications. It may be used in applications requiring level translation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally, with a diode connected in series with 5 V VDD, the ADG3257 may also be used in applications requiring 5 V to 3.3 V level translation. Table I. Truth Table 1. 0.1 ns propagation delay through switch 2. 2 switches connect inputs to outputs 3. Bidirectional operation 4. Ultralow power dissipation 5. 16-lead QSOP package BE H L L S X L H Function DISABLE A = B1 A = B2 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. ADG3257-SPECIFICATIONS1 (V Parameter DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current OFF State Leakage Current ON State Leakage Current Max Pass Voltage4 CAPACITANCE A Port OFF Capacitance B Port OFF Capacitance A, B Port ON Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A tPD Propagation Delay Matching6 Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Select Time S to A or B Enable Disable Max Data Rate DIGITAL SWITCH ON Resistance 4 CC = 5.0 V 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.) Min 2.4 -0.3 B Version Typ3 Max Unit V V A A A V pF pF pF pF Symbol VINH VINL II IOZ IOZ VP CA OFF CB OFF CA, CB ON CIN tPHL, tPLH5 tPZH, tPZL tPHZ, tPLZ tSEL_EN tSEL_DIS Conditions2 0 VIN 5.5 V 0 A, B VCC 0 A, B VCC VIN = VCC = 5 V, IO = -5 A f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VA = 0 V, CL = 50 pF VA = 0 V, CL = 50 pF CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 VA = 2 V p-p VA = 0 V IO = 48 mA, 15 mA, 8 mA, TA = 25C IO = 48 mA, 15 mA, 8 mA VA = 2.4 V IO = 48 mA, 15 mA, 8 mA, TA = 25C IO = 48 mA, 15 mA, 8 mA VA = 0 V 48 mA, 15 mA, 8 mA, TA = 25C VA = 0 V, 48 mA, 15 mA, 8 mA 3.9 0.01 0.01 0.01 4.2 7 5 11 4 +0.8 1 1 1 4.4 1 1 0.10 ns 0.0075 0.035 ns 5 7.5 ns 3.5 7 ns 8 5 933 12 8 ns ns Mbps RON 2 3 4 5 6 0.35 0.7 5.5 1 200 V A A 3 ON Resistance Matching RON 0.15 POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input7 3.0 ICC ICC Digital Inputs = 0 V or VCC VCC = 5.5 V, One Input at 3.0 V; Others at VCC or GND 0.001 NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 See Test Circuits and Waveforms. 3 All typical values are at T A = 25C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test. Specifications subject to change without notice. -2- REV. C ADG3257 SPECIFICATIONS1 (V Parameter CC = 3.3 V 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.) Conditions2 Min 2.0 -0.3 0 VIN 3.6 V 0 A, B VCC 0 A, B VCC VIN = VCC = 3.3 V, IO = -5 A f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VA = 0 V, CL = 50 pF VA = 0 V, CL = 50 pF CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 VA = 2 Vp-p VA = 0 V IO = 15 mA, 8 mA, TA = 25C VA = 1.7 V, IO = 15 mA, TA = 25C VA = 1.7 V, IO = 8 mA, TA = 25C B Version Typ3 Max Unit V V A A A V pF pF pF pF 0.10 0.04 9 8.5 12 9 ns ns ns ns ns ns Mbps Symbol VINH VINL II IOZ IOZ VP CA OFF CB OFF CA, CB ON CIN tPHL, tPLH5 tPZH, tPZL tPHZ, tPLZ tSEL_EN tSEL_DIS DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current OFF State Leakage Current ON State Leakage Current Max Pass Voltage4 CAPACITANCE A Port OFF Capacitance B Port OFF Capacitance A, B Port ON Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A tPD Propagation Delay Matching6 Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Select Time S to A or B Enable Disable Max Data Rate DIGITAL SWITCH ON Resistance 4 2.3 +0.8 0.01 1 0.01 1 0.01 1 2.6 2.8 7 5 11 4 1 1 0.01 5.5 4.5 8 6 933 RON 2 8 7 0.2 4 4.5 16.5 18 14 17 0.4 0.8 ON Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input7 RON VA = 0 V, 15 mA, 8 mA, TA = 25C VA = 0 V, 15 mA, 8 mA 3.0 V A A ICC ICC Digital Inputs = 0 V or VCC VCC = 3.3 V, One Input at 3.0 V; Others at VCC or GND 5.5 0.001 1 200 NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 See Test Circuits and Waveforms. 3 All typical values are at T A = 25C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical R ON of the switch and the load capacitance when driven by an ideal voltage source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. C -3- ADG3257 ABSOLUTE MAXIMUM RATINGS* (TA = 25C, unless otherwise noted.) PIN CONFIGURATION S1 1B1 2 1B2 3 1A 4 16 VCC 15 BE 14 4B1 VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V Digital Inputs to GND . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C QSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . 149.97C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300C IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . 235C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 13 4B2 TOP VIEW 2B1 5 (Not to Scale) 12 4A 2B2 6 11 3B1 2A 7 GND 8 10 3B2 9 3A ADG3257 PIN FUNCTION DESCRIPTIONS Mnemonic BE S Ax Bx Description Output Enable (Active Low) Port Select Port A, Inputs or Outputs Port B, Inputs or Outputs ORDERING GUIDE Model ADG3257BRQ Temperature Range -40C to +85C Package Descriptions RQ = 0.15" Quarter Size Outline Package (QSOP) Package Option RQ-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG3257 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. C Typical Performance Characteristics-ADG3257 20 TA = 25 C 16 16 15 VCC = 3.0V 12 RON - 20 TA = 25 C 20 VCC = 5V 12 RON - VCC = 5.0V 8 VCC = 4.5V 4 VCC = 5.5V 0 0 1 2 3 VA/VB - V 4 5 RON - VCC = 2.7V 10 8 +85 C 5 +25 C 4 VCC = 3.3V 0 0 0.5 1.0 1.5 2.0 VA/VB - V 2.5 3.0 0 0 1 2 3 VA/VB - V -40 C 4 5 TPC 1. ON Resistance vs. Input Voltage TPC 2. ON Resistance vs. Input Voltage TPC 3. ON Resistance vs. Input Voltage for Different Temperatures 20 VCC = 3V 10m TA = 25 C 1m VCC = 5V 5 TA = 25 C 4 VCC = 5.5V OUTPUT VOLTAGE - V 15 CURRENT - A 100 VCC = 5.0V 3 VCC = 4.5V 2 +85 C RON - 10 10 1 VCC = 3V 100n +25 C 5 1 -40 C 0 0 0.5 1.0 1.5 2.0 VA/VB - V 2.5 3.0 10n 0.1 1 10 100 1000 FREQUENCY - kHz 10000 0 0 1 2 3 4 INPUT VOLTAGE - V 5 TPC 4. ON Resistance vs. Input Voltage for Different Temperatures TPC 5. ICC vs. Enable Frequency TPC 6. Max Pass Voltage 3.6 TA = 25 C 3 OUTPUT VOLTAGE - V VCC = 3.6V 2 VCC = 3.3V VCC = 3.0V 1 40mV/DIV 267ps/DIV VCC = 5V VIN = 2V p-p 622MBPS 20dB ATTENUATION TA = 25 C 40mV/DIV 180ps/DIV VCC = 5V VIN = 2V p-p 933MBPS 20dB ATTENUATION TA = 25 C 0 0 0.5 1.0 1.5 2.5 2.0 INPUT VOLTAGE - V 3.0 3.5 TPC 7. Max Pass Voltage TPC 8. 622 Mbps Eye Diagram TPC 9. 933 Mbps Eye Diagram REV. C -5- ADG3257 2 VCC S1 OPEN RL PULSE1 GENERATOR VIN D.U.T. RT3 CL2 RL VOUT GND VCC APPLICATIONS Mixed Voltage Operation, Level Translation Bus switches can be used to provide a solution for mixed voltage systems where interfacing bidirectionally between 5 V and 3 V devices is required. To interface between 5 V and 3.3 V buses, an external diode is placed in series with the 5 V power supply as shown in Figure 4. VCC = 5V NOTES 1PULSE GENERATOR FOR ALL PULSES: t < 2.5ns, t < 2.5ns. F R 2C = INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES. L 3R IS THE TERMINATION RESISTOR; SHOULD BE EQUAL TO Z T OUT OF THE PULSE GENERATOR. BE Figure 1. Load Circuit VIH SWITCH INPUT VT 3.3V CPU/DSP/ MICROPROCESSOR/ MEMORY 3.3V TO 5V 3.3V TO 3.3V 5V MEMORY 5V I/O tPLH OUTPUT tPHL 0V VOH VT VOL Figure 2. Propagation Delay ENABLE CONTROL INPUTS DISABLE VIH VT 0V Figure 4. Level Translation Between 5 V and 3.3 V Devices The diode drops the internal gate voltage down to 4.3 V. The bus switch limits the voltage present on the output to VCC - external diode drop = VTH. Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V, the output voltage would be limited to 3.3 V with a logic high. V tPZL OUTPUT S1 @ 2 V CC LOW VCC VT tPLZ VCC VOL + VOL VOH VOH - 0V VOUT 5V SUPPLY 3.3V SWITCH OUTPUT tPZH OUTPUT S1 @ 2 V CC VT 0V tPHZ V Figure 3. Select, Enable, and Disable Times Table II. Switch S1 Condition 0V SWITCH INPUT 5V VIN Test tPLH, tPHL tPLZ, tPZL tPHZ, tPZH tSEL S1 OPEN 2 x VCC GND OPEN Figure 5. Input Voltage to Output Voltage Similarly, the device could be used to translate bidirectionally between 3.3 V to 2.5 V systems. In this case, there is no need for an external diode. The internal VTH drop is 1 V, so with a VCC = 3.3 V the bus switch will limit the output voltage to VCC - 1 V = 2.3 V. Table III. Test Conditions Symbol RL V CL VCC = 5 V 500 300 50 10% VCC = 3.3 V 500 300 50 10% Unit mV pF -6- REV. C ADG3257 3.3V VOUT 3.3V SUPPLY 2.5V SDRAM #1 SDRAM #2 ADG3257 2.5V 2.5V SWITCH OUTPUT 3.3V 2.5V SDRAM #7 0V SWITCH INPUT 3.3V VIN SDRAM #8 Figure 6. 3.3 V to 2.5 V Level Translation Using the ADG3257 Bus Switch Memory Switching BE LOGIC S This quad bus switch may be used to allow switching between different memory banks, thus allowing additional memory and decreasing capacitive loading. Figure 7 illustrates the ADG3257 in such an application. Figure 7. Allows Additional Memory Modules without Added Drive or Delay REV. C -7- ADG3257 OUTLINE DIMENSIONS 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches 0.193 BSC 16 9 0.154 BSC 1 8 0.236 BSC PIN 1 0.065 0.049 0.069 0.053 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8 0 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AB Revision History Location 4/03--Data Sheet changed from REV. B to REV. C. Page Updated Publication Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4/03--Data Sheet changed from REV. A to REV. B. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 06/02--Data Sheet changed from REV. 0 to REV. A. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -8- REV. C C02914-0-4/03(C) |
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